MOSFET
1.1
Introduction
The
metal-oxide semiconductor field-effect transistor (MOSFET) is a three-terminal
active device, which has many applications in both analog and digital
electronics. The three terminals are the source (S), the drain (D), and the gate
(G). The gate is insulated from the channel, which permits the gate-to-source
voltage to be either positive or negative without the flow of gate current for
both the n-channel and the p-channel devices.
There are two types of MOSFET's: the depletion mode
device and the enhancement mode device. In each, the current, which flows in
the drain-to-source channel, is a function of the voltage applied from gate to
source. In the depletion mode device, the channel is conducting when the
gate-to-source voltage is zero. In contrast, in the enhancement mode device,
the channel is non-conducting when the gate-to-source voltage is zero. For
enhancement mode devices, the drain current is zero until the gate-to-source voltage exceeds a value that
is known as the threshold voltage (Vt).
1.2
MOS Structure
The basis of MOS transistor is
a metal oxide semiconductor structure. The device input is called the 'gate'. Originally this was a metal
plate, although nowadays it is usually made
of polycrystalline silicon (commonly called poly or polysilicon). The oxide is
very pure silicon dioxide and it separates the gate from the semiconductor
materials; it acts as an insulator.
The semiconductor is very pure
silicon, which has been doped with relatively
small amounts of an impurity such that the impurity atoms can easily replace silicon atoms in the regular, fixed
crystal structure. Pure silicon is not a good conductor at room
temperature as there are very few electrons of negative charge. which acquire a
high enough energy to
break away from the silicon atoms. The electrons which escape are tree to move about the material and are
referred to as 'free charge carries'. They leave a vacancy or hole in the parent atom which now has a net positive charge.
Other electrons of lower energy move to fill these vacancies and
this movement of free carriers is equivalent to the movement of holes of
positive charge.
An n-type semiconductor is obtained by doping pure
silicon with an impurity processing one more
electron (in the outermost orbit) than silicon. This electron is only loosely,
bound to the impurity atom and can easily acquire enough energy to break away leaving the fixed impurity atom positively charged.
The freed electrons from the majority of
free charge in the material, significantly reducing it's resistively below that
of pure silicon. A few free holes
still exist and these are referred to as the 'minority charge carrier'.
A p-type semiconductor arises when the impurity atoms have
one fewer electrons in the outer orbit
than does silicon. These are thus a vacancy for an extra electron and electrons
move to fill these vacancies, causing the field impurity atoms to become negatively charged. This electron extraction is equivalent
to the injection of positive holes.
Thus the majority of free charge carries are holes and the minority charge
carries are electrons.
The semiconductor material of figure 1 consists of a
lightly doped p-type substrate and
heavily doped n-type regions, denoted n+ and called the source and
the drain which are located at each end of
the gate. Conventionally, the drain is the device output terminal and the source is the terminal that is
common to both the input and output circuits. It is
therefore usual to specify the devices input voltage as V, meaning Vg -Vs and its
output voltage as Vd, meaning Vd-Vs.
A terminal is connected to the bulk substrate and in NMOS
this is always connected to the most negative
voltage available. This is so that the diodes formed by the substrate-source and substrate-drain p-n junctions
are always reverse biased and hence never conduct.
1.2.1 MOS Structure in
Depletion
- A +ve Vgb applied to the gate of a MOS structure whose substrate is grounded produces E penetrating into the substrate.
- For a p-type substrate, E repels majority holes from the surface, creating a depletion region.
- Some minority electrons are attracted to the surface, but at low values of Vgb their numbers are not sufficient to cause much effect
- Charge balance is primarily +ve holes on gate, -ve ionized acceptors.
- This is termed depletion Operation.
1.2.2MOS
Structure
in Inversion
- At large Vgb, a dense inversion layer of electrons forms under the surface.
- Further increases in Vgb only change the density of the inversion layer.
- The potential at which the inversion layer dominates the substrate behavior is the threshold voltage Vt.
- This inversion layer will form the conductive channel between the source and drain of the MOSFET.
1.2.3
Electric Fields in the MOSFET:
Two distinct electric field distributions exist in the MOSFET structure:
— The transverse field is caused by the potential
difference between the conductive gate
and the substrate. This field supports the substrate depletion region and
inversion layer.
— The lateral field arises due to a non-zero source
to drain potential, and is (in the simple model) the main mechanism for
current flow in the MOSFET.
1.2.4 Threshold Voltage:
The input potential at which the surface just becomes
inverted is called the threshold voltage VT.
Below the threshold voltage an NMOS transistor is off and no current flows, while above the threshold the inversion
channel is established and the device conducts.
A detailed
analysis of the magnitude of the threshold voltage is complex. However, the factors determining Vt can be
appreciated from a consideration of the excess
charge within an NMOS device when the inversion layer is established. This is depicted
in figure 6.
The surface state charge Os, represents
positive charge trapped at the oxide semiconductor interface as a result of
imperfections at this surface. This, plus the gate charge Q must equal the
induced charge in the inversion channel Qc plus the impurity atom
charge Qd in the depletion region. Thus,
When the surface is just at the point of inversion, Qc = 0 and
In practice, VT has to overcome
some in built potential differences before the transistor is brought to the
edge of conduction. As a result, another two voltage terms have to be included
in the above expressions for Vt. Vdif represents the
voltage arising as a result of the difference between the gate and the
semiconductor material. Since silicon gates are used nowadays, Vdif is
small. The other voltage term Vr is the voltage across the depletion
region dust at the point of inversion; it is dependent upon the impurity
concentration and is usually less than 1 volt. Thus
If body is not connected to the source then the above equation becomes
1.2.5
Saturation Region:
In this region, Vds
> Vgs – VT. As the drain voltage across the
insulator at the drain drops and Vds = Vgs – VT . it is VT.
This is the voltage necessary to just support inversion, and this point on the Ids
verses Vds characteristics is called `pinch-off’.
At this point the inversion channel
ends just at the drain. As Vds
increase beyond pinch-off, the point at which cease moves away from
the drain.
The voltage difference along the
inversion channel from the source to where it ceases Vgs – VT, and the excess potential Vds = Vgs – VT is doped between
the end of the inversion channel
and the drain.. This creates a high eclectic field across this very short distance and the electrons from the inversion channel are
quickly swept across this area to the drain.
1.2.6 Resistive Region:
Here, Vds< Vgs – VT The voltage across the insulator
at the source is Vgs and
at the drain is Vgd (meaning Vg– Vd ). Although
the voltage across the insulator is not constant, a voltage in excess of VT exists
at all points across the oxide, causing the formation of a continuous inversion channel
between the drain and the source. It will be assumed that the increase in voltage along the
channel from the drain to the source is linear with distance.
The device structure therefore resembles an infinite number- of capacitances between the drain and the source, each one having a different voltage across it and therefore a different charge from its neighbors. The total charge included in the channel is the sum of the charge induced on each of these capacitances.
The device structure therefore resembles an infinite number- of capacitances between the drain and the source, each one having a different voltage across it and therefore a different charge from its neighbors. The total charge included in the channel is the sum of the charge induced on each of these capacitances.
1.2.7 n-Channel MOSFET with Vgs < VT
- With Vgs < VT, there is no inversion layer present under the surface.
- At Vds = 0, the source and drain depletion regions are symmetrical.
- A positive Vds reverse biases the drain substrate junction, hence the depletion region around the drain widens, and since the drain is adjacent to the gate edge, the depletion region widens in the channel.
- No current flows even for Vds > 0, since there is no conductive channel between the source and drain for Vgs < VT.
1.2.8 n-Channel
MOSFET With Vgs > VT , small Vds
- With Vgs > Vt, a conductive channel forms under the surface - a nonzero transverse field is present.
- Id is zero for Vds= 0 since no lateral field is present.
- For Vds > 0, transverse E is present and current flows
- The increased reverse bias on the drain substrate junction in contact with the inversion layer causes inversion layer density to decrease.
1.2.9 n-Channel
MOSFET With Vgs>VT, large Vds
(1) The point at
which the inversion layer density becomes very small (essentially zero) at
the drain end is termed pinch-off,
(2) The value of Vds at pinch-off is denoted Vds
(sat)
(3) Past pinch-off,
further increases in lateral electric field are absorbed by the creation of a narrow high field region with low carrier
density so if n is small E
is large).
1.3 Triode Region
In this region (Vgs> VT, and
Vds = Vgs - VT) the gate voltage
exceeds the threshold voltage and pulls negative charges toward the gate. This
results is an n-Channel whose width controls the current flow Id between the drain and
source.
where product of surface mobility of channel electrons and gate capacitance per unit area Cox in units of amps
per volts squared, W is the channel width and L is the channel
length.
1.4 Current Vs. Voltage Characteristic of an n-Channel MOSFET:
An important parameter in MOS transistors is the threshold voltage VT which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an n-channel device must be larger than some value VT before a conducting channel is induced. Similarly, a p-channel device (made on an n-type substrate with p-type source and drain implants or diffusions) requires a gate voltage more negative than some threshold value to induce the required positive charge (mobile holes) in the channel. The value of VT is controlled during device fabrication and typically lies in the range 0.5 to 3 Volts.
The characteristic
curves above indicate that there are three distinct regions of operation:
the cutoff region, the triode region, and the saturation region. The saturation
region is used if the MOSFET is to operate as an
amplifier. For operation as a switch, the cutoff
and triode regions are utilized. The device is cut off when Vgs< VT.
The
n-channel enhancement type MOSFET operates in the triode region when Vgs
is greater than VT and the drain voltage is lower than the gate
voltage by at least VT volts. In the triode region, the Id vs
Vds characteristics can be approximately described by the
relationship:
In which K is a device
parameter given by:
Where mobility of channel electron is a physical constant known as the electron
mobility (its value in this case applies for the electrons in the induced
n-channel), Cox (called the oxide capacitance) is the capacitance
per unit area of the gate-to-body capacitor for which the oxide layer serves as
dielectric, L is the length of the channel and W is its width. The aspect ratio
of the device(W/L) determines its conductivity parameter K which has the unit
A/V2.
If Vds is
sufficiently small so that the V2ds term in the above
equation (where the MOSFET is operating in the triode region) can be neglected,
then the Id vs Vds characteristics near the origin are
described by the following linear relationship,
The n-channel
enhancement-type MOSFET operates in the saturation region when Vgs is
greater than VT and the drain voltage does not fall below the gate
voltage by more than VT volts. In saturation , the MOSFET provides a
drain current whose value is independent of the drain voltage Vds and
is determined by the gate voltage Vgs according to the square-law
relationship.
MOSFET
Id vs Vds Characteristic:
1.
For Vgs<VT, ID = 0
2.
As Vds increases at a fixed Vgs, ID
increases in the triode region (due to the increased lateral field) also
causing the gate-to-channel voltage at the drain end to decrease.
3.
At some point, the gate-to-channel potential will drop below VT and
the channel will no longer be inverted at the drain end. At this point, the
channel is said to become pinched-off.
4.
Since the voltage at the drain end of the channel is VD,
pinch-off occurs at VGD = VT and this occurs when Vds
>Vgs - VT.
5.
At this point, further increases in drain current will not affect the
drain current and the device enters into the saturation region.
1.5
MOSEFT Operating Modes:
Two
basic operating modes of a MOSFET are
depletion mode and enhancement mode.
1.5.1Depletion
Mode:
For Vgs=
0, a conducting channel exists (ON state)
for a depletion type MOSFET. Its channel
conductivity is large. There is large ID(sat) = ID (Vgs
= 0).When
reverse Vgs is
applied, positive charges are induced in the channel at interface between
source and oxide which reduces the number of electrons available for channel
conductance.
So, the channel depleted of carriers and channel
conductivity lowers.ID decreases
as Vgs made more –ve. Eventually for a high –ve Vgs
the MOSFET turns into OFF state.
1.5.2Enhancement
Mode of Operation
For Vgs = 0, there is no
conducting channel (OFF state) for an enhancement type MOSFET. So, channel
conductivity is very small. No ID
flows since we have a n+-p-n+ channel structure (two oppositely opposed p-n junctions).
When forward VGS is
applied, an electric field induces in SiO2 and holes deposited on metal gate.
Electron charge appears in the source adjacent to oxide layer (drawn from n+
drain and source regions) through inversion. Channel is not
depleted and channel conductivity
is ON state like a parallel-plate capacitor.
MOS
Capacitance:
The gate of an MOS transistor is a good capacitor.
Indeed, its capacitance is necessary to attract charge to invert the channel,
so high gate capacitance is required to obtain high Ids. The gate
capacitance can be viewed as a parallel plate capacitor with the gate on top
and channel on bottom with the thin oxide dielectric between. Therefore, the
capacitance is
Cg
=CoxWL
Channel
Length Modulation:
Ideally, Ids is independent of Vds
for a transistor in saturation, making the transistor a perfect current source.
The reverse biased p-n junction between the drain and body forms a depletion
region with a width Ld that increases with Vdb. The
depletion region effectively shortens the channel length to
Leff
=L - Ld
Hence,
increasing Vds decreases the effective channel length. Shorter
channel length results I higher current; thus Ids increases Vds
in saturation. This can be crudely modeled by multiplying the eq…… by a
factor of (1+λVds).In the saturation region, we find
The
parameter λ is an empirical channel length modulation factor. As channel length
gets shorter, the effect of the channel length modulation factor becomes
relatively more important. Hence, λ is inversely dependent on channel length.
Velocity
Saturation and Mobility Degradation:
Carrier
drift velocity and hence current increase linearly with the lateral electric
field Elat=Vds/L between source and drain. This is only
true for weak fields; at high field strength, drift velocity rolls off due to
carrier scattering and eventually saturates at υsat, as shown in
Fig….The carrier velocity can be related to saturation current with the
following equation.
So,
the drain current is quadratically dependent on voltage without voltage and
linearly dependent when fully velocity saturated. For moderate supply voltages,
transistors operate in a region where the velocity no longer increases linearly
with field, but also is not completely saturated.
Subthreshold Conduction:
When
the gate electrode of a MOSFET is biased
below threshold voltage, such that the conducting channel is weakly inverted
the MOSFET is said to be in subthreshold regime. This regime is very important
since it is one of the two stationary operating states of MOSFETS in digital
applications. The ON-state of the MOSFET which corresponds a gate bias above
threshold, allows a significant drain current to pass through the device, while
the OFF-state, which corresponds to a subthreshold gate bias, should ideally
block all drain current. In practice there will always some leakage current in
the OFF-state owing to a finite amount of mobile charge at the
semiconductor-insulator interface and a finite injection rate of carriers from
the source into the channel.
Drain Induced Barrier Lowering:
If
small channel length MOSFETs are not scaled properly, and the source/drain junctions are too deep or the channel doping
is too low, there can be unintended electrostatic interactions between the
source and the drain known Drain Induced
Barrier Lowering (DIBL).This leads to punch-through leakage or breakdown
between the source and the drain, and loss of gate control. The phenomenon can
be understood from the fig where we have schematically plotted the surface
potential along the channel for along channel device and a short device. We see
that as the drain bias is increased, the conduction band edge (which reflects
the electron energies) in the drain is pulled down, and the drain-channel
depletion width expands. For a long channel MOSFET, the drain bias does not
affect the source-to-channel potential barrier, which corresponds to the
built-in potential of the source-channel p-n junction. Hence, unless the gate
bias is increased to lower this potential barrier, there is little drain
current. On the other hand, for a short channel MOSFET, as the drain bias is
raised and the conduction band edge in the drain is pulled down (with
concomitant increase of the drain depletion width), the source-channel
potential barrier is lowered due to DIBL. This can be shown numerically by a
solution of the two dimensional position equation in the channel region.
Simplistically, the ON-set of DIBL is sometimes considered to correspond to the
drain depletion region expanding and merging with the source depletion region,
and causing punch through breakdown between source and drain.
However,
it must be kept mind that DIBL ultimately caused by the lowering of the
source-junction potential barrier mellow the built-in potential. Hence, if we
get DIBL in a MOSFET for a grounded substrate, the problem can be mitigated by
applying a substrate reverse bias,
because that raises the potential barrier at the source end. This works in
spite of the fact that the drain depletion region interacts even more with the
source depletion region under such back bias. On the source-channel barrier is
lowered by DIBL, there can be significant drain leakage current, with the gate
being unable to shut it OFF.
Gate-Induced
Drain Leakage:
